System Verilog Assertion Control During Run Time

During our functional verification many times we want to control SV assertions, whether to make them part of the simulation or not. Below is the simple method using which we can control the assertions at run time. No need to modify the assertion or test bench file.


We can define one variable which can be used to control the assertion to be part of simulation or not  during run time. For example say  MODULE_ASSERT_CTRL defined in the same file where SV assertions are also defined.

using this variable we can write our assertion like below

logic MODULE_ASSERT_CTRL;
initial
       begin
             MODULE_ASSERT = $test$plusarg("MODULE_ASSERT_CTRL");
       end


property abcd;
             @osedge clk) disable iff(reset || MODULE_ASSERT)
              -----------
              -----------
endproperty
camp_per: assert property(abcd)

And during our simulation we can pass MODULE_ASSERT_CTRL as an argument like below. I used this with VCS simulator.

-simv_args  +MODULE_ASSERT_CTRL

So whenever we pass this argument with the simulation, the assertions would be disabled and reduce the burden on simulator.